#pragma ident "@(#)mmustat.txt 1.3 05/08/12 SMI" * 1.0 Introduction This document describes the hypervisor API to support MMU statistics collection on a Niagara-based system. This API is intended for Niagara-specific performance measurement. * 2.0 Hypervisor API for Niagara MMU statistics collection On Niagara, hypervisor maintains MMU statistics. Privileged code provides Hypervisor a buffer wherein these statistics can be collected. After the successful configuration of the buffer, it is continuously updated (hits increased and ticks updated). * 2.1 niagara_mmustat_conf API call To support the collection of Niagara MMU statistics the following function is offered: Entry: trap# FAST_TRAP function# NIAGARA_MMUSTAT_CONF (0x102) arg0 raddr Exit: ret0 status ret1 raddr Errors: ENORADDR Invalid raddr EBADALIGN raddr not aligned on 64-byte boundary EBADTRAP API not supported (all non-Niagara1 architectures) This function enables MMU statistic collection and supplies the buffer to deposit the results for the current virtual CPU. The real address of the buffer, raddr, is supplied in arg0. The return value, ret1, is the previously specified buffer, or zero for the first invocation. If raddr is zero MMU statistic collection is disabled for the current virtual CPU and any previously supplied buffer is no longer accessed. If an error is returned no statistics are collected (equivalent to passing an raddr of zero). The initial contents of the buffer should be zero otherwise the collected statistics will be meaningless. * 2.2 niagara_mmustat_info API call This function provides an idempotent mechanism to query the state and real address of the currently configured buffer. Entry: trap# FAST_TRAP function# NIAGARA_MMUSTAT_INFO (0x103) Exit: ret0 status ret1 raddr Errors: EBADTRAP API not supported (all non-Niagara1 architectures) The real address of the current buffer, raddr, or zero, if no buffer is defined, is returned in ret1. * 2.3 MMU statistic buffer format offset (bytes) size (bytes) field -------------- ------------ ----- 0x0 0x8 IMMU TSB hits ctx0, 8kb TTE 0x8 0x8 IMMU TSB ticks ctx0, 8kb TTE 0x10 0x8 IMMU TSB hits ctx0, 64kb TTE 0x18 0x8 IMMU TSB ticks ctx0, 64kb TTE 0x20 0x10 reserved 0x30 0x8 IMMU TSB hits ctx0, 4mb TTE 0x38 0x8 IMMU TSB ticks ctx0, 4mb TTE 0x40 0x10 reserved 0x50 0x8 IMMU TSB hits ctx0, 256mb TTE 0x58 0x8 IMMU TSB ticks ctx0, 256mb TTE 0x60 0x20 reserved 0x80 0x8 IMMU TSB hits ctxnon0, 8kb TTE 0x88 0x8 IMMU TSB ticks ctxnon0, 8kb TTE 0x90 0x8 IMMU TSB hits ctxnon0, 64kb TTE 0x98 0x8 IMMU TSB ticks ctxnon0, 64kb TTE 0xA0 0x10 reserved 0xB0 0x8 IMMU TSB hits ctxnon0, 4mb TTE 0xB8 0x8 IMMU TSB ticks ctxnon0, 4mb TTE 0xC0 0x10 reserved 0xD0 0x8 IMMU TSB hits ctxnon0, 256mb TTE 0xD8 0x8 IMMU TSB ticks ctxnon0, 256mb TTE 0xE0 0x20 reserved 0x100 0x8 DMMU TSB hit ctx0, 8kb TTE 0x108 0x8 DMMU TSB ticks ctx0, 8kb TTE 0x110 0x8 DMMU TSB hit ctx0, 64kb TTE 0x118 0x8 DMMU TSB ticks ctx0, 64kb TTE 0x120 0x10 reserved 0x130 0x8 DMMU TSB hit ctx0, 4mb TTE 0x138 0x8 DMMU TSB ticks ctx0, 4mb TTE 0x140 0x10 reserved 0x150 0x8 DMMU TSB hit ctx0, 256mb TTE 0x158 0x8 DMMU TSB ticks ctx0, 256mb TTE 0x160 0x20 reserved 0x180 0x8 DMMU TSB hit ctxnon0, 8kb TTE 0x188 0x8 DMMU TSB ticks ctxnon0, 8kb TTE 0x190 0x8 DMMU TSB hit ctxnon0, 64kb TTE 0x198 0x8 DMMU TSB ticks ctxnon0, 64kb TTE 0x1A0 0x10 reserved 0x1B0 0x8 DMMU TSB hit ctxnon0, 4mb TTE 0x1B8 0x8 DMMU TSB ticks ctxnon0, 4mb TTE 0x1C0 0x10 reserved 0x1D0 0x8 DMMU TSB hit ctxnon0, 256mb TTE 0x1D8 0x8 DMMU TSB ticks ctxnon0, 256mb TTE 0x1E0 0x20 reserved where "ticks" is the cumulative time spend handling the specified hit measured via deltas in the %tick register * 3.0 References For further information on the hypervisor/sun4v API, including calling conventions, status return values and error codes, see: FWARC case 2005/116 - sun4v core API.