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Date: Wed, 22 Aug 2007 15:38:15 -0400
From: Narayan Venkat <Narayan.Venkat@sun.com>
Subject: FWARC 2007/480: sun4v Cpu MD node property updates
Sender: Narayan.Venkat@sun.com
To: Firmware Arch <fwarc@sun.com>
Cc: Narayan Venkat <Narayan.Venkat@sun.com>,
        Wayne Mesard <Wayne.Mesard@sun.com>, hvrock-dev@sun.com
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I am sponsoring this fast-track case for Wayne Mesard. This case
adds optional properties to the sun4v Cpu node to inform the guest
about underlying CPU features.

This case will be approved for minor/micro/patch OS binding and
minor/micro binding for the firmware.

The document describing the new properties is available in the
materials directory at,

http://sac.sfbay.sun.com/arc/FWARC/2007/480/materials/one-pager.txt

The brief description of the changes are:

     Name        Tag        Req'd?    Description
      
----------------------------------------------------------------------
     hwcap-list  PROP_DATA  No        A list of strings identifying
                                      which ISA extensions are
                                      implemented in this processor.
                                      The currently defined values for
                                      constructing an 'hwcap-list' are:
                                       
fjfmau","fmaf","ASIBlkInit","vis2",
                                      "vis","popc","v8plus", "fsmuld",
                                      "div32","mul32". [*]

     memory-model-list
                 PROP_DATA  No        A list of strings identifying
                                      which memory models are supported,
                                      as per UA-2009 (or future revs of
                                      same) Appendix D (Formal
                                      Specification of the Memory
                                      Models).  Currently defined values
                                      are: "tso", "rmo" and "wc".  These
                                      are, respectively,
                                      "Total Store Order",
                                      "Relaxed Memory Order", and
                                      "Weak Consistency".



From sacadmin Thu Aug 30 11:38:56 2007
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Date: Thu, 30 Aug 2007 14:36:20 -0400
From: Narayan Venkat <Narayan.Venkat@Sun.COM>
Subject: Re: FWARC 2007/480: sun4v Cpu MD node property updates
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Hi

This case has timed out and hence is approved.  I will update the
IAM file. This case is approved for minor/micro/patch OS binding and
minor/micro binding for the firmware.

Thanks
-Narayan

On Aug 22, 2007, at 3:38 PM, Narayan Venkat wrote:

> I am sponsoring this fast-track case for Wayne Mesard. This case
> adds optional properties to the sun4v Cpu node to inform the guest
> about underlying CPU features.
>
> This case will be approved for minor/micro/patch OS binding and
> minor/micro binding for the firmware.
>
> The document describing the new properties is available in the
> materials directory at,
>
> http://sac.sfbay.sun.com/arc/FWARC/2007/480/materials/one-pager.txt
>
> The brief description of the changes are:
>
>     Name        Tag        Req'd?    Description
>      
> ----------------------------------------------------------------------
>     hwcap-list  PROP_DATA  No        A list of strings identifying
>                                      which ISA extensions are
>                                      implemented in this processor.
>                                      The currently defined values for
>                                      constructing an 'hwcap-list' are:
>                                       
> fjfmau","fmaf","ASIBlkInit","vis2",
>                                      "vis","popc","v8plus", "fsmuld",
>                                      "div32","mul32". [*]
>
>     memory-model-list
>                 PROP_DATA  No        A list of strings identifying
>                                      which memory models are  
> supported,
>                                      as per UA-2009 (or future revs of
>                                      same) Appendix D (Formal
>                                      Specification of the Memory
>                                      Models).  Currently defined  
> values
>                                      are: "tso", "rmo" and "wc".   
> These
>                                      are, respectively,
>                                      "Total Store Order",
>                                      "Relaxed Memory Order", and
>                                      "Weak Consistency".
>
>


