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Date: Fri, 05 Sep 2008 11:20:58 -0700
From: Hitendra Zhangada <Hitendra.Zhangada@Sun.COM>
Subject: Converting to Fast-track : 2008/398 - Hypervisor API for Transactional
 Memory Configuration
Sender: Hitendra.Zhangada@Sun.COM
To: Firmware ARC <fwarc@Sun.COM>
Cc: Shesha Sreenivasamurthy <Shesha.Sreenivasamurthy@Sun.COM>,
        Prashanth Sreenivasa <pks@Sun.COM>
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I am converting this case to fast-track case for Shesha Sreenivasamurthy.
This case defines a Hypervisor API function to provide a way the guest
can use Transactional Memory (TM).  See details in the attached
specification.

This case will be approved for minor/micro/patch OS binding
and minor/micro binding for the firmware.

The case timer is set to expire on September 12, 2008.


Thanks.


-- 
Hitendra Zhangada
=============================================
SPS Common SW Features Engineering
Software Group, Sun Microsystems, Inc.
Work Ph# (858) 625 3757, Ext. x53757
SUN Internal homepage http://esp.west/~hitu


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1. Introduction
This document specifies a Hypervisor API function to provide a way the guest
can use Transactional Memory (TM). This specification provides description for
a single function that the guest can use to change the way memory transactions
are handled.

2. Transactional Memory description:
	TM is a way of providing concurrency control on a system. It serves
	as an alternative to legacy locking mechanisms. This is implemented
	as an extension of multi-processor cache coherency protocol. Using
	this function guest can control when memory transactions need to be
	executed based on architectural specifications and when to fail them
	unconditionally. Modification is on a per virtual cpu basis. To alter
	the way all the virtual cpus in a system handle memory transactions,
	guest need to call this function once per virtual cpu. TM is enabled
	by default. This API is called once during boot.

3.  rk_tm_enable:
	Trap#:		FAST_TRAP
	Group#:		API_GROUP_TM (0x80)
		Major#:	1
		Minor#:	0
	Function#:	TM_ENABLE (0x180)
	arg0:		Zero or Non-Zero Value
	ret0:		EOK:	Success
			EINVAL:	Failure

	This function is implemented only on processors that supports TM.
	Therefore it is a part of CPU group. When enabled, memory
	transactions fail or succeed based on architectural specification.
	When disabled, all TM instructions are treated a legal instructions
	but the memory transactions are failed unconditionally. To disable
	a zero is passed and to enable a Non-zero value is passed in arg0.

4. Interfaces:
    4.1 Imported Interfaces:

      Interface                 Classification	      Comments
      ==============================================================
      HV APIs                      Committed       FWARC/2005/116

    4.2 Exported Interfaces:

      Interface                   Classification	   Comments
      ===================================================================
      TM_ENABLE API function        Committed      Function 0x180, group
                                              	    0x80 as defined in
                                                    section 3


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From sacadmin Fri Sep 12 15:52:37 2008
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Date: Fri, 12 Sep 2008 15:52:33 -0700
From: Hitendra Zhangada <Hitendra.Zhangada@sun.com>
Subject: Re: Converting to Fast-track : 2008/398 - Hypervisor API for
 Transactional Memory Configuration
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        Prashanth Sreenivasa <pks@sun.com>
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Hitendra Zhangada wrote:
> I am converting this case to fast-track case for Shesha Sreenivasamurthy.
> This case defines a Hypervisor API function to provide a way the guest
> can use Transactional Memory (TM).  See details in the attached
> specification.
>
> This case will be approved for minor/micro/patch OS binding
> and minor/micro binding for the firmware.
>
> The case timer is set to expire on September 12, 2008.
>

This case has timed out and is now approved.

I am update IAM file and HV registry later.


Thanks.



-- 
Hitendra Zhangada
=============================================
SPS Common SW Features Engineering
Software Group, Sun Microsystems, Inc.
Work Ph# (858) 625 3757, Ext. x53757
SUN Internal homepage http://esp.west/~hitu


