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Date: Fri, 05 Sep 2008 22:51:38 -0700
From: Hitendra Zhangada <Hitendra.Zhangada@sun.com>
Subject: Converting to Fast-track : 2008/401 - MMU TLB page search Hypervisor
 API
Sender: Hitendra.Zhangada@sun.com
To: Firmware ARC <fwarc@sun.com>
Cc: Shesha Sreenivasamurthy <Shesha.Sreenivasamurthy@sun.com>,
        Prashanth Sreenivasa <pks@sun.com>,
        Charles Kunzman <Charles.Kunzman@sun.com>,
        James Barnette Jr <Richard.Barnette@sun.com>
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I am converting this case to fast-track case for Charles Kunzman.
This case adds new, optional hypervisor API calls and associated
MD properties for sun4v platforms.  API group MMU_EXT (0x4) is
created for the APIs defined by this case. See details in the
attached specification (only updated sections 4 and 5 of the
one-pager are included as the specification).

This case will be approved for minor/micro/patch OS binding
and minor/micro binding for the firmware.

The case timer is set to expire on September 12, 2008.


Thanks.


-- 
Hitendra Zhangada
=============================================
SPS Common SW Features Engineering
Software Group, Sun Microsystems, Inc.
Work Ph# (858) 625 3757, Ext. x53757
SUN Internal homepage http://esp.west/~hitu




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4. Technical Description:
    4.1. Details:
	As the capabilities of MMUs for SPARC processors increase, it is
	no longer feasible in all cases to implement a TLB with a single
	associative lookup.  UltraSPARC processors now allow for the
	following inputs into the TLB lookup:
	  * A Partition id (number of bits depends on CPU)
	  * A tag from the VA (up to 51 bits)
	  * A private context number (up to 16 bits)
	  * One or more shared context numbers (up to 16 bits each)
	Additionally, the TLB must be able to recognize mappings to as
	many as 8 distinct page sizes.

	The total number of inputs means that for CPU hardware to find
	the mapping for a given memory access, multiple TLB probes may
	be required.  With the CPU performing multiple probes, it may
	be important for software to control either the number or order
	of the probes:
	  * Controlling the number of probes may improve performance by
	    eliminating unnecessary probes.
	  * Controlling the order of probes may improve performance by
	    searching frequently accessed mappings before searching
	    rarer ones.
	  * Controlling the order of probes can make it possible to
	    have multiple mappings for the same address without
	    ambiguitiy, by indicating which mapping has precedence.

	The API below provides control over the order and number of
	probes performed by the MMU, where each probe can be different
	in the following parameters:
	  * Which context register (private or shared) is used to
	    determine the context number.
	  * The page size of the mapping to probe for.

    4.1.1. MD property updates:
    4.1.1.1. Default search order:
	On systems supporting the TLB search API, there is a default
	search order that is in effect for all MMU accesses (privileged
	and non-privileged, instruction and data) if the guest does not
	use the new API.  The characteristics of that default search
	order are indicated by existing properties in the MD node:

    Name			         Tag
	    Description
    ----------------------------------------------------------------------
    mmu-#shared-contexts		PROP_VAL
        A 64-bit unsigned integer giving the number of primary and secondary
        shared context registers supported by this virtual CPU's MMU and
        the number of shared contexts in the default search order.
        If not present the default value is assumed to be 0. 

    mmu-page-size-list			PROP_VAL
        A 64-bit unsigned integer treated as a bit field describing the page
        sizes that may be used on this virtual CPU and page sizes supported in
        the default search order. Page size encodings are defined according to
        the sun4v Architecture Specification. A bit N in this field, if set,
        indicates that sun4v defined page size with encoding N is available
        for use.

	The default search order searches every combination of context
	register and page size specified in these two properties.  The
	order of the default search is not specified.

	These properties exist merely to provide compatibility for
	guests that do not use the TLB search API, and have no meaning
	for a virtual CPU that has changed its search order.

    4.1.1.2. New MD properties:
	The properties below are part of the CPU node.  All of these
	properties are required to be present for any CPU that supports
	the new API calls described in this specification.  None are
	present in the CPU node unless the CPU supports the calls.

    Name			         Tag
	    Description
    ----------------------------------------------------------------------
    mmu-search-#shared-contexts		PROP_VAL
	    The number of shared contexts (in addition to the private
	    context) supported in search list entries.  The
	    interpretation is equivalent to the mmu-#shared-contexts
	    property; however, the value may be different.

    mmu-search-page-size-list		PROP_VAL
	    The set of page sizes supported in search list entries.  The
	    format is equivalent to the mmu-page-size-list property;
	    however, the value may be different.

    mmu-max-search-order		PROP_VAL
	    The maximum number of entries allowed in a search list.  All
	    search lists terminate after this many entries, with or
	    without a terminator entry with its enable bit clear.

    mmu-priv-search-unified		PROP_VAL
    mmu-non-priv-search-unified		PROP_VAL
	    Indicates whether the privileged and non-privileged search
	    orders have unified or separate I- and D- search orders.  A
	    value of 1 indicates the search order is unified (I- and D-
	    search orders must be the same).  A value of 0 indicates
	    that the I- and D- search orders may be different.

    4.1.1.3. Notes and caveats for MD properties:
	The mmu-page-size-list and mmu-search-page-size-list properties
	are distinct, and may have different values; similarly for
	mmu-#shared-contexts and mmu-search-#shared-contexts.  To
	understand why, consider the case of a CPU that supports 8 page
	sizes and 1 shared context (meaning 2 contexts total).  To
	search every context for every page size requires 8*2=16 probes.
	If mmu-max-search-order is less than 16, the default search
	order cannot search every valid combination.

	To guarantee compatibility for guests that don't use (or know
	about) TLB search orders, the product of the number of sizes in
	mmu-page-size-list and mmu-#shared-contexts must be selected to
	be less than mmu-max-search-order.  To achieve this, in some
	cases the default search order may disable page sizes, context
	registers, or both.


    4.1.2. API specification:    
    4.1.2.1. Search lists for MMU translations and MMU flag :
	The new API introduces a new data type for specifying MMU search
	lists.  A search list is the real address of an array of
	two-byte search entries; the size of the array is specified in
	the mmu-max-search-order property.  Each entry specifies a
	context register and page size for a TLB probe, plus an enable
	bit.

	To guarantee a hit for a particular mapping, the mapping must be
	installed normally in a TSB, or with one of the mapping API
	calls; additionally there must be an entry in the applicable TLB
	search order specifying the page size for the mapping and a
	context register that holds the context number of the mapping.

	To guarantee a miss on a particular address it is necessary to
	demap the address fully.  If a mapping is valid with the current
	context registers and TSB contents, it may hit even if the
	mapping cannot be found using the current applicable search
	order.

	The ordering of entries in the searchlist is significant in
	two ways:
	  * Probes to entries earlier in the search order may perform
	    faster than probes to later entries.
	  * For the non-privileged search list, if the MMU has two
	    mappings for the same address distinguished by the size
	    of the mappings, a page size that occurs earlier in
	    the search order takes precedence over a size later in
	    the search order.

	Mappings in the MMU must be unique except in the case of
	non-privileged mappings distinguished by page size.  This
	includes the case of the same VA being mapped differently by two
	different context registers, even if one of the context
	registers is not used in the search order.  (This is the same
	restriction documented in section 14.12.2 of the UltraSPARC
	Architecture 2007 specification).

	The API calls for configuring a search order allow specifying
	flags indicating whether the search order is for instruction
	accesses, data accesses, or both.  However, in some cases,
	there may be a unified search order for both instruction and
	data accesses.  In this case, the appropriate property in the MD
	(either mmu-priv-search-unified or mmu-non-priv-search-unified)
	will indicate that separate search lists are not available.

	The individual bit fields of each search list table entry are
	laid out as follows:
	    | Enable | reserved | Context | reserved | Size |
	      [15]     [14:11]    [10:7]    [6:3]      [2:0]

	Enable - The Enable field is 1 to indicate a valid search entry.
	    If a search entry has its Enable bit cleared, that entry
	    and all higher-indexed entries are ignored.
	Context - The Context field is 0 to indicate CONTEXT0 (the
	    private context), 1 to indicate CONTEXT1 (the 1st shared
	    context), and so forth.  The value of the field cannot
	    exceed mmu-search-#shared-contexts (see below).  If shared
	    contexts are not supported, the field must be 0.  The
	    Context field is only supported for non-privileged search
	    lists; privileged search lists must set Context to 0
	    (indicating only CONTEXT0 is searched).
	Size - The Size field encodes a standard page size field:
		PageSize = 1 << (3 * Size + 13)
	    The size must be one of the valid sizes indicated in
	    mmu-search-page-size-list.
        
        
    The MMU Flag argument for each API is the same as defined by core API
    bindings (FWARC/2005/116, see link to Virtual Machine Specification in
    section 5 below) but is duplicated here for quick reference.
    
    The flags argument applies the API operation to instruction translations
    if bit 1 is set, and in addition applies the API operation to data
    translation entries if bit 0 is set. For every API service requiring
    a flags argument, at least one of bit 0 and/or bit 1 must be set.
    

    4.1.2.2. API function call summary:
    MMU_EXT (0x4) is created for the MMU extension APIs defined below.
    These are the calls for configuring the new MMU mapping resources:

    #Name			Group#	Trap#	Func#	Major#	Minor#
    #====			======	=====	=====	======	======
    MMU_GET_NONPRIV_SEARCH	0x4	0x80	0x104	1	0
    MMU_SET_NONPRIV_SEARCH	0x4	0x80	0x105	1	0
    MMU_GET_PRIV_SEARCH		0x4	0x80	0x106	1	0
    MMU_SET_PRIV_SEARCH		0x4	0x80	0x107	1	0


    4.1.2.3.
	trap: FAST_TRAP
	function: MMU_GET_NONPRIV_SEARCH
	arg0: searchlist
	arg1: flags
	ret0: status

	The flags argument indicates whether to get the search order
	for instruction or data accesses.  Only one type of access
	can be gotten with a single call.

	Fill in the provided search list with the current search list
	for the calling virtual CPU, as set by the
	MMU_SET_NONPRIV_SEARCH call.

	Errors:
	EINVAL      flags is 0, or indicates both I- and D- accesses.
	ENORADDR    The search list is not a valid real address.

    4.1.2.4.
	trap: FAST_TRAP
	function: MMU_SET_NONPRIV_SEARCH
	arg0: searchlist
	arg1: flags
	ret0: status

	The flags argument indicates whether the search order applies
	to instruction or data accesses, or both.  The encoding is the
	same as for other MMU calls, such as MMU_MAP_ADDR.  If the value
	of mmu-non-priv-search-unified is 1, the flags parameter must
	specify both I- and D- searches together.

	Set the calling virtual CPU's non-privileged search list.  This
	search list will be used for both instruction and data lookups
	performed in non-privileged mode, or when using any of the
	"AS_IF_USER" ASIs in privileged mode.

	(N.B. the search list applies to non-privileged TLB lookups,
	regardless of the context to be searched.  This is different
	from TSB lookup, which searches based on the context number).

	Errors:
	EINVAL      flags is 0
	EINVAL      mmu-non-priv-search-unified is 1, and flags does not
		    specify both I- and D- accesses.
	EINVAL	    A page size in the search list isn't valid.
	EINVAL	    A context register number in the search list isn't
		    valid.
	ENORADDR    The search list is not a valid real address.

    4.1.2.5.
	trap: FAST_TRAP
	function: MMU_GET_PRIV_SEARCH
	arg0: searchlist
	arg1: flags
	ret0: status

	The flags argument indicates whether to get the search order
	for instruction or data accesses.  Only one type of access
	can be gotten with a single call.

	Fill in the provided search list with the calling virtual CPU's
	current search list for privileged translations, as set by the
	MMU_SET_PRIV_SEARCH call.

	Errors:
	EINVAL      flags is 0, or indicates both I- and D- accesses.
	ENORADDR    The search list is not a valid real address.

    4.1.2.6.
	trap: FAST_TRAP
	function: MMU_SET_PRIV_SEARCH
	arg0: searchlist
	arg1: flags
	ret0: status

	The flags argument indicates whether the search order applies
	to instruction or data accesses, or both.  The encoding is the
	same as for other MMU calls, such as MMU_MAP_ADDR.  If the value
	of mmu-priv-search-unified is 1, the flags parameter must
	specify both I- and D- searches together.

	Set the calling virtual CPU's search list for privileged
	translations.

	Errors:
	EINVAL      flags is 0
	EINVAL      mmu-priv-search-unified is 1, and flags does not
		    specify both I- and D- accesses.
	EINVAL	    A page size in sizelist isn't valid.
	EINVAL	    A Context field in sizelist is not 0.
	ENORADDR    The search list is not a valid real address.

    4.2. Bug/RFE Number(s):
	N/A

    4.3. In Scope:
	N/A

    4.4. Out of Scope:
	N/A

    4.5. Interfaces:
    4.5.1. Imported Interfaces:
    Interface			Classification	Comments
    ====================================================================
    Machine Description (MD)	Sun Private	Defined by FWARC/2005/115
    data structures

    sun4v core API		Sun Private	Core APIs defined by
						FWARC/2005/116

    4.5.2. Exported Interfaces:
    Interface			Classification	Comments
    ====================================================================
    mmu-search-#size-bits	Committed	MD property
    mmu-search-#context-bits	Committed	MD property
    mmu-search-page-size-list	Committed	MD property
    mmu-max-search-order	Committed	MD property
    mmu-non-priv-search-unified	Committed	MD property
    mmu-priv-search-unified	Committed	MD property
    MMU_EXT			Committed	API group 0x4, v1.0
    MMU_GET_NONPRIV_SEARCH	Committed	API call
    MMU_SET_NONPRIV_SEARCH	Committed	API call
    MMU_GET_PRIV_SEARCH		Committed	API call
    MMU_SET_PRIV_SEARCH		Committed	API call

    4.6. Doc Impact:
	The UltraSPARC Virtual Machine Specification must be updated to
	reflect this addition.

    4.7. Admin/Config Impact:
	No impact.

    4.8. HA Impact:
	No impact.

    4.9. I18N/L10N Impact:
	No impact.

    4.10. Packaging & Delivery:
	No impact.

    4.11. Security Impact:
	No impact.

    4.12. Dependencies:
	This interface depends on underlying hardware that provides
	the capability.  The API and associated properties will not be
	present on platforms that don't support the capability.

5. Reference Documents:
	UltraSPARC Architecture 2007 Specification
	http://opensparc-t2.sunsource.net/specs/UA2007-current-draft-HP-EXT.pdf

	UltraSPARC Virtual Machine Specification
	http://opensparc-t1.sunsource.net/specs/Hypervisor-api-current-draft.pdf

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Date: Fri, 12 Sep 2008 15:53:07 -0700
From: Hitendra Zhangada <Hitendra.Zhangada@Sun.COM>
Subject: Re: Converting to Fast-track : 2008/401 - MMU TLB page search
 Hypervisor API
In-reply-to: <48C21A6A.10007@sun.com>
Sender: Hitendra.Zhangada@Sun.COM
To: Firmware ARC <fwarc@Sun.COM>
Cc: Shesha Sreenivasamurthy <Shesha.Sreenivasamurthy@Sun.COM>,
        Prashanth Sreenivasa <pks@Sun.COM>,
        Charles Kunzman <Charles.Kunzman@Sun.COM>,
        James Barnette Jr <Richard.Barnette@Sun.COM>
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Hitendra Zhangada wrote:
> I am converting this case to fast-track case for Charles Kunzman.
> This case adds new, optional hypervisor API calls and associated
> MD properties for sun4v platforms.  API group MMU_EXT (0x4) is
> created for the APIs defined by this case. See details in the
> attached specification (only updated sections 4 and 5 of the
> one-pager are included as the specification).
>
> This case will be approved for minor/micro/patch OS binding
> and minor/micro binding for the firmware.
>
> The case timer is set to expire on September 12, 2008.

This case has timed out and is now approved.

I am update IAM file and HV registry later.


Thanks.

>


-- 
Hitendra Zhangada
=============================================
SPS Common SW Features Engineering
Software Group, Sun Microsystems, Inc.
Work Ph# (858) 625 3757, Ext. x53757
SUN Internal homepage http://esp.west/~hitu


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Subject: Re: Converting to Fast-track : 2008/401 - MMU TLB page search
 Hypervisor API
To: Hitendra.Zhangada@sun.com, fwarc@sun.com
Cc: Charles.Kunzman@sun.com, Richard.Barnette@sun.com,
        Shesha.Sreenivasamurthy@sun.com, pks@sun.com
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>This case has timed out and is now approved.

Hitendra, there's still offline discussion going
on regarding this case and not all issues have been
resolved.

Please revert the status back to waiting need spec
until all the issues are resolved.

Thanks,
David


From sacadmin Wed Sep 17 13:54:24 2008
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Date: Wed, 17 Sep 2008 13:51:54 -0700
From: Hitendra Zhangada <Hitendra.Zhangada@Sun.COM>
Subject: Re: Converting to Fast-track : 2008/401 - MMU TLB page search
 Hypervisor API
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        Shesha.Sreenivasamurthy@Sun.COM, pks@Sun.COM
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On 09/17/08 13:27, David Kahn wrote:
>> This case has timed out and is now approved.
>>     
>
> Hitendra, there's still offline discussion going
> on regarding this case and not all issues have been
> resolved.
>
> Please revert the status back to waiting need spec
> until all the issues are resolved.
>   

Wait, the case timed out last Friday.  The discussions are happening
this week and so I am not sure we can stop project team from moving
forward.  They had Solaris C-team commitment to get the ARC case
approved and API code integrated into Solaris.  It won't be fair to
the project team to undo an ARC approval action.  ARC had whole
week to review the material and this case had no discussions in
that one week window.

I am not saying that these discussions should not happen but
the changes to the ARC approved specifications can be dealt
with a new case to amend what has been approved.

I want to make sure we are doing the right thing by revering
the case status to "waiting need spec" for a closed approved
case and also want to make sure what this means to the
project team. 

Lets discuss this before we take an action on this case.


Thanks.


> Thanks,
> David
>
>   


-- 
Hitendra Zhangada
====================================
SPS Common SW Features Engineering
Software Group, Sun Microsystems, Inc.
Sun Ph# (858) 625 3757, Sun Ext. x53757
Internal homepage http://esp.west/~hitu


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<head>
  <meta content="text/html;charset=ISO-8859-1" http-equiv="Content-Type">
</head>
<body bgcolor="#ffffff" text="#000000">
On 09/17/08 13:27, David Kahn wrote:
<blockquote cite="mid:200809172027.m8HKRRJi021333@noho.sfbay.sun.com"
 type="cite">
  <blockquote type="cite">
    <pre wrap="">This case has timed out and is now approved.
    </pre>
  </blockquote>
  <pre wrap=""><!---->
Hitendra, there's still offline discussion going
on regarding this case and not all issues have been
resolved.

Please revert the status back to waiting need spec
until all the issues are resolved.
  </pre>
</blockquote>
<br>
Wait, the case timed out last Friday.&nbsp; The discussions are happening<br>
this week and so I am not sure we can stop project team from moving<br>
forward.&nbsp; They had Solaris C-team commitment to get the ARC case<br>
approved and API code integrated into Solaris.&nbsp; It won't be fair to<br>
the project team to undo an ARC approval action.&nbsp; ARC had whole<br>
week to review the material and this case had no discussions in<br>
that one week window.<br>
<br>
I am not saying that these discussions should not happen but<br>
the changes to the ARC approved specifications can be dealt<br>
with a new case to amend what has been approved.<br>
<br>
I want to make sure we are doing the right thing by revering<br>
the case status to "waiting need spec" for a closed approved<br>
case and also want to make sure what this means to the<br>
project team.&nbsp; <br>
<br>
Lets discuss this before we take an action on this case.<br>
<br>
<br>
Thanks.<br>
<br>
<br>
<blockquote cite="mid:200809172027.m8HKRRJi021333@noho.sfbay.sun.com"
 type="cite">
  <pre wrap="">
Thanks,
David

  </pre>
</blockquote>
<br>
<br>
<pre class="moz-signature" cols="72">-- 
Hitendra Zhangada
====================================
SPS Common SW Features Engineering
Software Group, Sun Microsystems, Inc.
Sun Ph# (858) 625 3757, Sun Ext. x53757
Internal homepage <a class="moz-txt-link-freetext" href="http://esp.west/~hitu">http://esp.west/~hitu</a>
</pre>
</body>
</html>

--Boundary_(ID_2Gbe4eCtOxY+TRBhXo1FpA)--

From sacadmin Wed Sep 17 15:56:52 2008
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Date: Wed, 17 Sep 2008 15:56:49 -0700
From: David Kahn <David.Kahn@sun.com>
Subject: Re: Converting to Fast-track : 2008/401 - MMU TLB page search
 Hypervisor API
In-reply-to: <48D16DEA.6040908@Sun.COM>
To: Hitendra Zhangada <Hitendra.Zhangada@sun.com>
Cc: David Kahn <dmk@noho.sfbay.sun.com>, fwarc@sun.com,
        Charles.Kunzman@sun.com, Richard.Barnette@sun.com,
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Hitendra Zhangada wrote:
> On 09/17/08 13:27, David Kahn wrote:
>>> This case has timed out and is now approved.
>>>     
>>
>> Hitendra, there's still offline discussion going
>> on regarding this case and not all issues have been
>> resolved.
>>
>> Please revert the status back to waiting need spec
>> until all the issues are resolved.
>>   
> 
> Wait, the case timed out last Friday.

With unresolved issues. The timeout was incorrect.

-David

From sacadmin Wed Sep 17 16:12:07 2008
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Date: Wed, 17 Sep 2008 16:11:57 -0700
From: Hitendra Zhangada <Hitendra.Zhangada@sun.com>
Subject: Re: Converting to Fast-track : 2008/401 - MMU TLB page search
 Hypervisor API
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On 09/17/08 15:56, David Kahn wrote:
>
>
> Hitendra Zhangada wrote:
>> On 09/17/08 13:27, David Kahn wrote:
>>>> This case has timed out and is now approved.
>>>>     
>>>
>>> Hitendra, there's still offline discussion going
>>> on regarding this case and not all issues have been
>>> resolved.
>>>
>>> Please revert the status back to waiting need spec
>>> until all the issues are resolved.
>>>   
>>
>> Wait, the case timed out last Friday.
>
> With unresolved issues. The timeout was incorrect.

FYI.  There were ZERO discussion on this case once it was submitted
as fast-track till it timed out. 

The mail thread that is going on was started by me BEFORE the case
was converted to fast-track.  I decided to go ahead with case submission
after some discussions with few developers.  Everyone on the mail thread
also received the fast-track notice.   The mail thread got resurrected
this week when Richard sent reply to my original mail.  The mail
thread itself is/was not part of the FWARC review process.

I just want to know above facts. 


My suggestion is to have a offline meeting to talk about the issues
and come to a common understanding of the issues, resolve them if
possible and determine the next course of action.

Note that re-opening this case may result into delaying of SN putback
to Solaris.  I don't agree that they should suffer from this because
of lack of review/discussions after case was submitted for review.

So, yes I am not agreeing with you on re-opening this case unless
we have an offline meeting to discuss the issues first.  As per ARC
process, the timer has expired and so case has been approved.


Can we have that meeting?   I am ready to organize it.



Thanks.



>
> -David


-- 
Hitendra Zhangada
====================================
SPS Common SW Features Engineering
Software Group, Sun Microsystems, Inc.
Sun Ph# (858) 625 3757, Sun Ext. x53757
Internal homepage http://esp.west/~hitu


From sacadmin Wed Sep 17 16:28:43 2008
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Date: Wed, 17 Sep 2008 16:28:25 -0700
From: David Kahn <David.Kahn@sun.com>
Subject: Re: Converting to Fast-track : 2008/401 - MMU TLB page search
 Hypervisor API
To: Hitendra Zhangada <Hitendra.Zhangada@sun.com>
Cc: fwarc@sun.com, Charles.Kunzman@sun.com, Richard.Barnette@sun.com,
        Shesha.Sreenivasamurthy@sun.com, pks@sun.com
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Hitendra Zhangada wrote:

> The mail thread that is going on was started by me BEFORE the case
> was converted to fast-track.  I decided to go ahead with case submission
> after some discussions with few developers.

As sponsor of the case and owner of the case, we knew
there was at least one unresolved issue before the submission.

That issue should not have been ignored no matter where it
was raised.

Now there are additional issues being raised. Had the
initial approval been delayed until those unresolved
issues were resolved, then these new issues may have
been discussed before the incorrect time-out.

-David

From sacadmin Wed Sep 17 16:48:43 2008
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Date: Wed, 17 Sep 2008 16:48:13 -0700
From: Hitendra Zhangada <Hitendra.Zhangada@sun.com>
Subject: Re: Converting to Fast-track : 2008/401 - MMU TLB page search
 Hypervisor API
In-reply-to: <48D19299.5020906@sun.com>
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On 09/17/08 16:28, David Kahn wrote:
>
>
> Hitendra Zhangada wrote:
>
>> The mail thread that is going on was started by me BEFORE the case
>> was converted to fast-track.  I decided to go ahead with case submission
>> after some discussions with few developers.
>
> As sponsor of the case and owner of the case, we knew
> there was at least one unresolved issue before the submission.

I took Greg's comments as his opinion.  He expressed it to
me in IM and via e-mail but he did not argue about it.
I am not sure if that was a real issue since when I asked
to chime in on FWARC alias he did not send mail which
I interpreted as he is fine with it and there are no concerns
from him about the proposed change (this happened
2 days after the submission on Sunday - Sept. 7th).

>
> That issue should not have been ignored no matter where it
> was raised.

If I had interpreted as an issue then it would not have been ignored.

>
> Now there are additional issues being raised. Had the
> initial approval been delayed until those unresolved
> issues were resolved, then these new issues may have
> been discussed before the incorrect time-out.

Whatever might have happed here, because of my lack
of getting this as an issue form Greg, or new issues uncovered
from the mail thread, but fact is that between the time-out
window there were no discussions at ARC level.  You can
look at the mail file to confirm that.

As I said before, better way to handle this would be to
talk about it. IMO, e-mail is not the best way to discuss
the issues.

I am not willing to re-open the case.  If you feel strongly
about it then please own the case from me and do what
you thing is appropriate.


Sorry.


>
> -David


-- 
Hitendra Zhangada
====================================
SPS Common SW Features Engineering
Software Group, Sun Microsystems, Inc.
Sun Ph# (858) 625 3757, Sun Ext. x53757
Internal homepage http://esp.west/~hitu


From sacadmin Wed Sep 17 18:48:34 2008
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Date: Wed, 17 Sep 2008 21:48:28 -0400
From: Eric Sharakan <Eric.Sharakan@sun.com>
Subject: Re: Converting to Fast-track : 2008/401 - MMU TLB page search
 Hypervisor API
In-reply-to: <48D1973D.8030602@Sun.COM>
Sender: Eric.Sharakan@sun.com
To: Hitendra Zhangada <Hitendra.Zhangada@sun.com>
Cc: fwarc@sun.com, Charles.Kunzman@sun.com, Richard.Barnette@sun.com,
        Shesha.Sreenivasamurthy@sun.com, pks@sun.com
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FWIW, the emails from Greg & myself both started out with the caveat  
that we're asking about implementation issues, not architectural  
ones.  Also that email thread (purposely IMHO) excluded the fwarc  
alias for exactly this reason.

If those are the issues at contention here, I don't believe they  
should hold up the case.

This is just my opinion.  If this winds up coming to a vote, as a  
FWARC intern, I would have no voting rights...

-Eric

On Sep 17, 2008, at 7:48 PM, Hitendra Zhangada wrote:

> On 09/17/08 16:28, David Kahn wrote:
>>
>>
>> Hitendra Zhangada wrote:
>>
>>> The mail thread that is going on was started by me BEFORE the case
>>> was converted to fast-track.  I decided to go ahead with case  
>>> submission
>>> after some discussions with few developers.
>>
>> As sponsor of the case and owner of the case, we knew
>> there was at least one unresolved issue before the submission.
>
> I took Greg's comments as his opinion.  He expressed it to
> me in IM and via e-mail but he did not argue about it.
> I am not sure if that was a real issue since when I asked
> to chime in on FWARC alias he did not send mail which
> I interpreted as he is fine with it and there are no concerns
> from him about the proposed change (this happened
> 2 days after the submission on Sunday - Sept. 7th).
>
>>
>> That issue should not have been ignored no matter where it
>> was raised.
>
> If I had interpreted as an issue then it would not have been ignored.
>
>>
>> Now there are additional issues being raised. Had the
>> initial approval been delayed until those unresolved
>> issues were resolved, then these new issues may have
>> been discussed before the incorrect time-out.
>
> Whatever might have happed here, because of my lack
> of getting this as an issue form Greg, or new issues uncovered
> from the mail thread, but fact is that between the time-out
> window there were no discussions at ARC level.  You can
> look at the mail file to confirm that.
>
> As I said before, better way to handle this would be to
> talk about it. IMO, e-mail is not the best way to discuss
> the issues.
>
> I am not willing to re-open the case.  If you feel strongly
> about it then please own the case from me and do what
> you thing is appropriate.
>
>
> Sorry.
>
>
>>
>> -David
>
>
> -- 
> Hitendra Zhangada
> ====================================
> SPS Common SW Features Engineering
> Software Group, Sun Microsystems, Inc.
> Sun Ph# (858) 625 3757, Sun Ext. x53757
> Internal homepage http://esp.west/~hitu
>


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